This invention relates generally to computer systems, and more particularly to the arbitration mechanism for accessing a system bus of a computer system.
As it is known in the art, computer systems generally include at least one central processing unit (CPU) module, a main memory for storing data, at least one input/output (I/O) module, and a system bus coupling the aforementioned devices to the CPU module. The system bus typically includes data, address, and control lines. The CPU module often includes a processor for executing instructions and a cache memory for storing data and instructions which are readily accessible to the processor. The I/O module may be used to connect the computer system to many different types of devices, including other computer systems or secondary memory. Secondary memory is generally large and may include magnetic tape drives, disk drives, etc.
Often, the main memory includes a plurality of independent memory modules each having an interface to the system bus. The CPU can generally access cache memory more quickly than main memory and main memory more quickly than secondary memory. Each memory module contains semiconductor chips having a predetermined number of memory cells. The chips are often referred to as RAM, Random Access Memory, or DRAM, Dynamic Random Access Memory, in that each storage location is randomly addressable, as distinguished from other types of memory devices such as magnetic tape or disk which are sequentially accessible, in that a number of storage locations are scanned before reaching the desired addressed location.
Generally each memory module and I/O module responds to a different address range within the overall address range of the computer system. The size of each I/O module's address range depends on the size of the secondary memory to which it is connected and the mechanism used to convert system bus addresses into secondary memory addresses. The size of each memory module's address range corresponds to the number of addressable locations on the module. The starting address of a module's address range may be determined by virtue of the position (i.e., backplane slot) in which the module is placed within the computer system, or the starting address may be assigned through the use of memory configuration software and hardware which determines the number of addressable locations of each memory module in the system prior to assigning address ranges.
CPUs, as well as other commander modules such as the I/O interface, are capable of initiating transactions (read, write, etc.) on the system bus. Upon power-up, the CPU's cache memory is initialized and ready to be loaded with data from main memory or secondary memory. The CPU's processor loads the cache memory with needed instructions and data both at power-up and during processing as new data and instructions are needed. During processing the needed data may be in another CPU's cache memory or in main or secondary memory, also, data may be required to be written back into memory, main or secondary, prior to reading new data into cache memory. In any case, the CPU needs to gain control of the system bus in order to initiate a transaction on the system bus to access the data or instructions.
In order to initiate a transaction on the system bus, a CPU first gains control of the system bus which is often accomplished by arbitrating for the bus. There are typically two types of arbitration schemes; central arbitration and distributed arbitration. In a distributed arbitration scheme, all commander modules (i.e., modules capable of requesting control of the system bus) independently monitor all system bus control request signals to determine whether a transaction has been requested, and if so, which commander module is to be granted control of the system bus. In a central arbitration scheme, a central arbiter receives each commander module's request for system bus control (i.e., each commander module does not receive the other commander modules' request signals) and grants control of the system bus to one of the commander modules who requested such control.
Because CPU processors do not attempt to gain control of the system bus until they determine that they need to initiate a transaction on the system bus, the time required for arbitration is directly added to the time required to complete a transaction. Where the transaction is a read or write to memory, the memory latency includes the time required for arbitration.